1. Field of the Invention
This invention relates to silicon-on-insulator (SOI) structures, and more particularly, to radiation hardening of integrated circuits build upon SOI structures.
2. Background Description
Much work has been spent developing integrated circuits based on silicon-on-insulator technology. The SOI structure of a very thin silicon film on an insulating substrate, shown in FIG. 1, results in advantages such as faster circuit speeds, reduced power consumption, and smaller circuits.
Although SOI technology has these many advantages, it is at a disadvantage relative to bulk silicon for hardness against total dose radiation. The presence of the buried insulator layer creates an additional oxide that must be hardened. As a result of its thickness, sufficient amounts of positive charge are trapped in the insulator following total dose radiation. The charge accumulation results in increased device leakage and threshold voltage shifts.
A method to radiation harden bulk silicon devices is disclosed in U.S. patent application Ser. No. 06/393,012 filed Jun. 28, 1982 to Edenfeld et al., entitled "Method to Improve Radiation Hardness of Field Oxide". This application is commonly assigned to the same owner as the present application, the teaching of which are herein incorporated by reference. What would be desirable, is a method whereby an SOI structure can be formed such that the buried oxide traps only a very low net negative charge after total dose radiation exposure. In hardening SOI structures for total dose applications, two variations of the SOI structure need to be considered, a thin film fully depleted (FD) structure and a thick film SOI structure being partially depleted (PD). The difference between the FD and PD, is that when the FD transistor is turned off, the depletion regions formed by the transistor gate and buried oxide overlap, depleting the entire silicon film and the transistor body. In partially depleted transistors, these regions do not overlap, thus, leaving a neutral region in the body. As a result of these differences, charges generated in the buried oxide are reflected proportionally in the transistor gate in fully depleted transistors but not in partially depleted transistors. For both transistors, charges in the buried oxide attract carriers to the body/buried oxide interface. When sufficient carriers are attracted to the interface, a parasitic conductive path is formed, resulting in increases in the transistor leakage. Due to the softness of conventional buried oxides, this leakage path occurs at very low radiation dosages, making it difficult to use fully depleted SOI technology in applications requiring radiation hardened electronics (e.g., missiles, nuclear reactors).
Several methods of improving the useful total radiation dose for SOI circuits are known. These techniques include the use of thicker silicon films and employing thinner buried oxides. As described above, the use of thicker silicon films improves the total dose hardness because the film is only partially depleted. Thus, the gate charge is not coupled to the buried oxide charge. Furthermore, with a thicker silicon film, the parasitic back channel leakage can be reduce by the use deep, high dosage ion implantation. It is very difficult to obtain sufficiently steep implant profiles with very thin silicon films. Additionally, this approach has the significant drawback that the body of the transistor is neutral and has a floating electrical potential. This results in the turn-on of the parasitic bipolar transistor formed by the source/body/drain of the device. To minimize the leakage caused by the transistor, the body of the transistor must be grounded either by a separate contact, or by a strap to the source. However, this results in a technology that is not compatible with bulk VLSI designs. Furthermore, many of the benefits of SOI, such as high transconductance, sharp transistor turn-on slopes and circuit density improvements are lost with partially depleted SOI.
Another potential hardening approach is to use thinner buried oxides. However, in fully depleted structures, the front gate threshold voltage is capacitively coupled to the buried oxide. Thus, thinning the buried oxide reduces the amount of charge that it traps, however, its capacitance goes up proportionally. Thus, essentially the same voltage shift in seen by the front gate.
What is needed, is a means to dope the buried oxide layer so as to produce a large number of recombination centers, such that the net trapped charge after total dose radiation is zero. An approach of implanting impurities into the SOI structure after it has been fabricated results in the amorphizing of the entire silicon film in order to implant the required energy and dose to form the recombination centers. The use of different insulating layers, such as an oxynitride layer doesn't work because it is difficult to form and control.